1. Field of the Invention
The present invention is directed to a plastic molded chip carrier package and a method of fabricating the same, and more particularly to a plasic package having a plurality of I/O pins and an integrally embeded conductor member for electrical interconnection of the chip to the individual I/O pins, and to a method of fabricating such a package.
2. Description of the Prior Art
Plastic chip carrier packages have been widely accepted in the art to replace ceramic packages for their feasibility of incorporating a plurality of I/O pins at the time of molding the package and for thermal compatibility with conventionally printed-circuit boards on which the packages are frequently required to be directly mounted. Such plastic packages have been proposed, for example, in U.S. Pat. No. 4,618,739 in which a chip carrier is molded from a suitable plastic material to integrally include a plurality of I/O pins. This package requires a separately formed metallized layer which should be bonded onto the molded chip carrier for interconnection of the I/O pins and a chip to be disposed centrally of the carrier, adding the bonding process to the fabrication of the package with accompanied difficulty for secure registration of conductor lines on the metallized layer with the corresponding I/O pins. The employment of the separately formed metallized layer inherently poses a problem that the conductor lines may fail to be securely connected to the respective I/O pins due to possible poor bonding between the metallized layer and the molded chip carrier. In this respect, the prior plastic packages suffer from rather complicated fabrication process as well as reduced reliability in the connection beween the conductor lines of the metallized layer and the respective I/O pins.